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ls3c5000 specification

key features

- loongson instruction set architecture (loongarch® ) 
- high-end multi-way: up to 16 socket with 256-core cc-numa interconnection structure. 
- excellent computing performance: measured over 900 points with spec cpu2006 result on 4 socket server.
- efficient virtualization: over 95% of kvm computing efficiency
- high-speed interconnection: multi-level hierarchical cache coherence protocol for efficient local and cross-chip access. 
- high bandwidth of memory: 4 memory channels per socket, providing sufficient bandwidth.
- supporting extended i/o: dual-bridge chipset support on multi-socket server




frequency

2.0-2.2 ghz

peak computing speed

560 gflops

number of cores

16

processor core

64-bit superscalar processor core la464; supporting loongarch® instruction set architecture; supporting 128/256-bit vector instructions; 4-issue out-of-order execution; 4 fixed-point units, 2 vector units, and 2 memory access units

high-speed cache

each processor core contains a 64kb private l1 instruction cache and a 64kb private l1 data cache; each processor core contains a 256kb private l2 cache; all processor cores share a 32mb l3 cache.

memory controller

four 72-bit ddr4-3200 controllers; supporting ecc

high-speed i/o

4 hypertransport 3.0 controllers; supporting cache coherent non–uniform memory access (cc-numa)

other i/o

1 spi, 1 uart, 3 i2c, 1 avs, 16 gpio interfaces

power management

supporting dynamic shutdown of clocks of main modules; supporting dynamic frequency scaling in main clock domains; supporting dynamic voltage scaling in main voltage domains.

typical power consumption

150w@2.2ghz

ls3c5000 manual

ls3c5000 application

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