- loongson instruction set architecture (loongarch® )
- measured single-core in spec cpu 2006 base result over 26
- measured memory bandwidth over 25 gb/s with ddr4-3200 interface
- unified ecosystem compatibility: real-time binary translation supports of applications from different isas
- fine-grained power management: built-in power control core for dynamic voltage and frequency scaling
peak computing speed
number of cores
64-bit superscalar processor core la464; supporting loongarch® instruction set architecture; supporting 128/256-bit vector instructions;4-issue out-of-order execution;4 fixed-point units, 2 vector units, and 2 memory access units
each processor core contains a 64kb private l1 instruction cache and a 64kb private l1 data cache; each processor core contains a 256kb private l2 cache; all processor cores share a 16mb l3 cache.
two 72-bit ddr4-3200 controllers; supporting ecc
2 hypertransport 3.0 controllers; supporting cache coherent non–uniform memory access (cc-numa)
1 spi, 1 uart, 2 i2cs, 16 gpio interfaces
supporting dynamic shutdown of clocks of main modules; supporting dynamic frequency scaling in main clock domains; supporting dynamic voltage scaling in main voltage domains.
typical power consumption